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9-95 cat25cxxx supervisory circuits with spi serial e 2 prom, precision reset controller and watchdog timer features n 10 mhz spi compatible n 1.8 to 6.0 volt operation n hardware and software protection n zero standby current n low power cmos technology n spi modes (0,0 &1,1) n commercial, industrial and automotive temperature ranges n active high or low reset outputs C precision power supply voltage monitoring C 5v, 3.3v, 3v and 1.8v options n watchdog timer on cs cs cs cs cs n 1,000,000 program/erase cycles n 100 year data retention n self-timed write cycle n 8-pin dip/soic, 16-pin soic and 14-pin tssop n page write buffer n block write protection C protect 1/4, 1/2 or all of e 2 prom array n programmable watchdog timer n built-in inadvertent write protection C v cc lock out ? 1998 by catalyst semiconductor, inc. characteristics subject to change without notice advanced description the cat25cxxx is a single chip solution to three popular functions of eeprom memory, precision reset controller and watchdog timer. the eeprom memory is a 2k/4k/8k/16k/32k-bit spi serial cmos e 2 prom internally organized as 256x8/512x8/1024x8/2048x8/ 4096x8 bits. catalysts advanced cmos technology substantially reduces device power requirements. the 2k/4k devices feature a 16-byte page write buffer. the 8k/16k/32k devices feature a 32-byte page write buffer.the device operates via the spi bus serial inter- face and is enabled though a chip select ( cs ). in addition to the chip select, the clock input (sck), data in (si) and data out (so) are required to access the device. the reset function of the 25cxxx protects the system during brown out and power up/down condtions. during system failure the watchdog timer feature pro- tects the microcontroller with a reset signal. the cat25cxxx is designed with software and hardware write protection features including block lock protec- tion. the device is available in 8-pin dip, 8-pin soic, 16- pin soic and 14-pin tssop packages. cs nc 1 2 3 4 14 13 12 11 nc nc nc 5 6 710 9 8 nc sck v ss si nc wp vcc reset /reset so 15 16 nc nc pin configuration dip package (p) soic package (s16) tssop package (u14) soic package (s) v ss so wp v cc reset /rese t sck si 1 2 3 4 8 7 6 5 cs cs wp reset /reset vcc nc nc nc nc so nc nc v ss sck si 1 2 3 4 5 6 7 8 9 10 11 12 13 14 so wp cs v cc sck si 1 2 3 4 8 7 6 5 v ss reset /reset
9-96 cat25cxxx stock no. 21085-01 4/98 advanced pin functions pin name function so serial data output sck serial clock wp write protect v cc +1.8v to +6.0v power supply v ss ground cs chip select si serial data input reset/ reset reset i/o nc no connect block diagram reliability characteristics symbol parameter min. max. units reference test method n end (3) endurance 1,000,000 cycles/byte mil-std-883, test method 1033 t dr (3) data retention 100 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 power-up timing (1)(2) symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1v to v cc +1v. sense amps shift registers spi control logic word address buffers i/o control e 2 prom array column decoders xdec high voltage/ timing control so 25cxxx f02.1 status register block protect logic control logic data i n storage si cs wp reset/ reset sck reset controller watchdog high precision v cc monitor
9-97 cat25cxxx stock no. 21085-01 4/98 advanced d.c. operating characteristics v cc = +1.8v to +6.0v, unless otherwise specified. limits symbol parameter min. typ. max. units test conditions i cc1 power supply current 5 ma v cc = 5v @ 5mhz (operating write) so=open; cs=vss i cc2 power supply current 0.4 ma v cc = 5.5v (operating read) f clk = 5mhz i sb power supply current 0 m a cs = v cc (standby) v in = v ss or v cc i li input leakage current 2 m a i lo output leakage current 3 m av out = 0v to v cc , cs = 0v v il (3) input low voltage -1 v cc x 0.3 v v ih (3) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 0.4 v v oh1 output high voltage v cc - 0.8 v v ol2 output low voltage 0.2 v 1.8v v cc <2.7v v oh2 output high voltage v cc -0.2 v i ol = 150 m a i oh = -100 m a absolute maximum ratings* temperature under bias ................. C55 c to +125 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to ground (1) ............ C2.0v to +v cc +2.0v v cc with respect to ground ............... C2.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100 ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. note: (1) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. 4.5v v cc <5.5v i ol = 3.0ma i oh = -1.6ma
9-98 cat25cxxx stock no. 21085-01 4/98 advanced limits 1.8, 2.5 4.5v-5.5v test symbol parameter min. max. min. max. units conditions t su data setup time 50 10 ns v ih = 2.4v t h data hold time 50 20 ns c l = 100pf t wh sck high time 200 40 ns v ol = 0.8v t wl sck low time 200 40 ns v oh = 2.0v f sck clock frequency dc 2 dc 10 mhz t lz hold to output low z 50 50 ns t ri (1) input rise time 2 2 m s t fi (1) input fall time 2 2 m s t hd hold setup time 100 40 ns t cd hold hold time 100 40 ns c l = 100pf t wc write cycle time 10 5 ms t v output valid from clock low 200 80 ns t ho output hold time 0 0 ns t dis output disable time 250 75 ns t hz hold to output high z 100 50 ns t cs cs high time 250 100 ns t css cs setup time 250 100 ns t csh cs hold time 250 100 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. a.c. characteristics c l = 50pf figure 1. sychronous data timing valid in v ih v il t css v ih v il v ih v il v oh v ol hi-z t su t h t wh t wl t v t cs t csh t ho t dis hi-z cs sck si so
9-99 cat25cxxx stock no. 21085-01 4/98 advanced functional description the cat25cxxx supports the spi bus data transmis- sion protocol. the synchronous serial peripheral inter- face (spi) helps the cat25cxxx to interface directly with many of todays popular microcontrollers. the cat25cxxx contains an 8-bit instruction register. (the instruction set and the operation codes are detailed in the instruction set table) after the device is selected with cs going low, the first byte will be received. the part is accessed via the si pin, with data being clocked in on the rising edge of sck. the first byte contains one of the six op-codes that define the operation to be performed. pin description si: serial input si is the serial data input pin. this pin is used to input all wp wp wp wp wp : write protect wp is the write protect pin. the write protect pin will allow normal read/write operations when held high. when wp is tied low and the wpen bit in the status register is set to 1, all write operations to the status register are inhibited. wp going low while cs is still low will interrupt a write to the status register. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit is set to 0. instruction opcode operation wren 0000 0110 enable write operations wrdi 0000 0100 disable write operations rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 x011 (1) read data from memory write 0000 x010 (1) write data to memory instruction set reset/ reset reset reset reset reset : reset i/o these are open drain pins and can be used as reset trigger inputs. by forcing a reset condition on the pins the device will initiate and maintain a reset condition. re- set pin must be connected through a pull-down and reset pin must be connected through a pull-up device. cs cs cs cs cs : chip select cs is the chip select pin. cs low enables the cat25cxxx and cs high disables the cat25cxxx. cs high takes the so output pin to high impedance and forces the devices into a standby mode (unless an internal write operation is underway) the cat25cxxx draws zero current in the standby mode. a high to low transition on cs is required prior to any sequence being initiated. a low to high transition on cs after a valid write sequence is what initiates an internal write cycle. note: (1) x=o for 25c02x/08x/16x/32x. x=a8 for 25c04x 76543210 wpen x wd1 wd0 bp1 bp0 wel rdy status register opcodes, byte addresses, and data to be written to the 25cxxx. input data is latched on the rising edge of the serial clock. so: serial output so is the serial data output pin. this pin is used to transfer data out of the 25cxxx. during a read cycle, data is shifted out on the falling edge of the serial clock. sck: serial clock sck is the serial clock pin. this pin is used to synchro- nize the communication between the microcontroller and the 25cxxx. opcodes, byte addresses, or data present on the si pin are latched on the rising edge of the sck. data on the so pin is updated on the falling edge of the sck.
9-100 cat25cxxx stock no. 21085-01 4/98 advanced the wpen (write protect enable) is an enable bit for the wp pin. the wp pin and wpen bit in the status register control the programmable hardware write protect fea- ture. hardware write protection is enabled when wp is low and wpen bit is set to high. the user cannot write to the status register, (including the block protect bits and the wpen bit) and the block protected sections in the memory array when the chip is hardware write protected. only the sections of the memory array that are not block protected can be written. hardware write protection is disabled when either wp pin is high or the wpen bit is zero. the watchdog timer bits, wd0 and wd1, select the watchdog time-out period. these nonvolatile bits are programmed with the wrsr instruction. status register bits array address protection bp1 bpo protected 0 0 none no protection 0 1 25c02x: c0-ff quarter array protection 25c04x: 180-1ff 25c08x: 0300-03ff 25c16x: 0600-07ff 25c32x: 0c00-0fff 1 0 25c02x: 80-ff half array protection 25c04x: 100-1ff 25c08x: 0200-03ff 25c16x: 0400-07ff 25c32x: 0800-0fff 1 1 25c02x: 00-ff full array protection 25c04x: 000-1ff 25c08x: 0000-03ff 25c16x: 0000-07ff 25c32x: 0000-0fff block protection bits wd1 wd0 watchdog timer time-out (typical) 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled watchdog timer bits status register the status register indicates the status of the device. the rdy (ready) bit indicates whether the cat25cxxx is busy with a write operation. when set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. this bit is read only.the wel (write enable) bit indicates the status of the write enable latch . when set to 1, the device is in a write enable state and when set to 0 the device is in a write disable state. the wel bit can only be set by the wren instruction and can be reset by the wrdi instruction. the bpo and bp1 (block protect) bits indicate which blocks are currently protected. these bits are set by the user issuing the wrsr instruction. the user is allowedto protect quarter of the memory, half of the memory or the entire memory by setting these bits. once protectedthe user may only read from the protected portion of the array. these bits are non-volatile.
9-101 cat25cxxx stock no. 21085-01 4/98 advanced figure 2. wren instruction timing device operation for the memory function write enable and disable the cat25cxxx contains a write enable latch. this latch must be set before any write operation. the device powers up in a write disable state when v cc is applied. wren instruction will enable writes (set the latch) to the device. wrdi instruction will disable writes (reset the latch) to the device. disabling writes will protect the device against inadvertent writes. read sequence the part is selected by pulling cs low. the 8-bit read instruction is transmitted to the cat25cxxx, followed by the 16-bit address for 25c08x/16x/32x (only 10-bit addresses are used for 25c08x, 11-bit addresses are used for 25c16x, and 12-bit addresses are used for 25c32x. the rest of the bits are don't care bits) and 8- bit address for 25c02x/04x (for the 25c04x, bit 3 of the read data instruction contains address a8). after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. the data stored in the memory at the next address can be read sequentially by continu- ing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address sk si cs so 00000 110 high-z protected unprotected status wpen wp wp wp wp wp wel blocks blocks register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable write protect enable operation write sequence the cat25cxxx powers up in a write disable state. prior to any write instructions, the wren instruction must be sent to cat25cxxx. the device goes into w rite enable state by pulling the cs low and then clocking the wren instruction into cat25cxxx. the cs must be brought high after the wren instruction to enable writes to the device. if the write operation is initiated immediately after the wren instruction without cs being brought high, the data will not be written to the array because the write enable latch will not have been properly set. also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level. after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefi- nitely. the read operation is terminated by pulling the cs high. to read the status register, rdsr instruction should be sent. the contents of the status register are shifted out on the so line. the status register may be read at any time even during a write cycle. read sequece is illustrated in figure 4. reading status register is illustrated in figure 5.
9-102 cat25cxxx stock no. 21085-01 4/98 advanced byte write once the device is in a write enable state, the user may proceed with a write sequence by setting the cs low, issuing a write instruction via the si line, followed by the 16-bit address for 25c08x/16x/32x (only 10-bit ad- dresses are used for 25c08x, 11-bit addresses are used for 25c16x, and 12-bit addresses are used for 25c32x. the rest of the bits are don't care bits) and 8- bit address for 25c02x/04x (for the 25c04x, bit 3 of the read data instruction contains address a8). program- ming will start after the cs is brought high. the low to high transition of the cs pin must occur during the sck low time, immediately after clocking the least significant bit of the data. figure 6 illustrates byte write sequence. during an internal write cycle, all commands will be ignored except the rdsr (read status register) in- struction. the status register can be read to determine if the write cycle is still in progress. if bit 0 of the status register is set at 1, write cycle is in progress. if bit 0 is set at 0, the device is ready for the next instruction. page write the cat25cxxx features page write capability. after the initial byte, the host may continue to write up to 16 bytes of data to the cat25c02x/04x and 32 bytes of data for 25c08x/16x/32x. after each byte of data received, lower order address bits are internally incremented by one; the high order bits of address will remain constant.the only restriction is that the x (x=16 for 25c02x/04x and x=32 for 25c08x/16x/32x) bytes must reside on the same page. if the address counter reaches the end of the page and clock continues, the counter will roll over to the first address of the page and overwrite any data that may have been written. the cat25cxxx is automatically returned to the write dis- able state at the completion of the write cycle. figure 8 illustrates the page write sequence. to write to the status register, the wrsr instruction should be sent. only bit 2, bit 3 and bit 7 of the status register can be written using the wrsr instruction. figure 7 illustrates the sequence of writing to status register. figure 4. read instruction timing sk si cs so reset 0000001 1 byte address* 012345678910 2021222324252627282930 7 6 5 4 3 2 1 0 *please check the instruction set table for address figure 3. wrdi instruction timing sk si cs so 0 0 000100 high-z 25c128 f05
9-103 cat25cxxx stock no. 21085-01 4/98 advanced figure 7. wrsr timing 25c128 f08 012345678 10 911121314 6 74 53210 cs sck si so instruction data i n figure 6. write instruction timing sk si cs so 0 0 0 0 0 0 1 0 address d7 d6 d5 d4 d3 d2 d1 d0 012345678 2122232425262728293031 figure 5. rdsr timing 25c128 f09 012345678 10 911121314 6 74 53210 cs sck si so high impedance msb data out
9-104 cat25cxxx stock no. 21085-01 4/98 advanced device operation for the supervisory circuit reset controller description the cat25cxxx provides a precision reset control- ler that ensures correct system operation during brown- out and power-up/down conditions. it is configured with open drain reset outputs. during power-up, the reset outputs remain active until v cc reaches the v th threshold and will continue driving the outputs for approximately 200ms (t purst ) after reaching v th. after the t purst timeout interval, the device will cease to drive reset outputs. at this point the reset outputs will be pulled up or down by their respective pull up/pull down devices. during power-down, the reset outputs will begin driving active when v cc falls below v th. the reset outputs will be valid so long as v cc is >1.0v (v rvalid ). the reset pins are i/os; therefore, the cat25cxxx can act as a signal conditioning circuit for an externally applied reset. the inputs are level triggered; that is, the reset input in the 25cxxx will initiate a reset timeout after detecting a high and the reset input in the 25cxxx will initiate a reset timeout after detecting a low. watchdog timer the watchdog timer provides an independent protec- tion for microcontrollers. during a system failure, the cat25cxxx will respond with a reset signal after a time out period (the time out period is defined by the watchdog timer bits wd0 an d wd1) for lack of activity. 25cxxx is designed with the watchdog timer feature on the cs input. for the 25cxxx, if the microcontroller does not toggle the cs pin within the time out period the watchdog timer times out. this will generate a reset condition on reset outputs. the watchdog timer is cleared by any transition on cs . as long as the reset signal is asserted, the watchdog timer will not count and will stay cleared. reset threshold voltage from the factory the 25cxxx is offered in six different variations of reset threshold voltages. they are 4.50- 4.75v, 4.25-4.50v, 3.00-3.15v, 2.85-3.00v, 2.55-2.70v and 1.7-1.8v. to provide added flexibility to design engineers using this product, the 25cxxx is designed with an additional feature of programming the reset threshold voltage. this allows the user to change the existing reset threshold voltage to one of the other five reset threshold voltages. once the reset threshold voltage is selected it will not change even after cycling the power, unless the user uses the programmer to change the reset threshold voltage. however, the programming function is available only through third party programmer manufacturers. please call catalyst for a list of programmer manufacturers who support this function. figure 8. page write instruction timing sk si cs so 0 0 0 0 0 0 1 0 address data byte 1 012345678 212223 24-31 32-39 data byte 2 data byte 3 data byte n
9-105 cat25cxxx stock no. 21085-01 4/98 advanced symbol parameter min. max. units t glitch glitch reject pulse width 100 ns v rt reset threshold hystersis 15 mv v olrs reset output low voltage (i olrs =1ma) 0.4 v v ohrs reset output high voltage vcc-0.75 v reset threshold (vcc=5v) 4.50 4.75 (25cxxx-45) reset threshold (vcc=5v) 4.25 4.50 (25cxxx-42) reset threshold (vcc=3.3v) 3.00 3.15 (25cxxx-30) reset threshold (vcc=3.3v) 2.85 3.00 (25cxxx-28) reset threshold (vcc=3v) 2.55 2.70 (25cxxx-25) reset threshold (vcc=1.8v) 1.70 1.80 (25cxxx-17) t purst power-up reset timeout 130 270 ms t rpd v th to reset output delay 5 m s v rvalid reset output valid 1 v reset circuit characteristics v v th figure 9. reset output timing glitch t v cc purst t purst t rpd t rvalid v v th reset reset rpd t
9-106 cat25cxxx stock no. 21085-01 4/98 advanced notes: (1) the device used in the above example is a 25c161si-30te13 (reset, soic, industrial temperature, 3.0-3.15 reset threshold voltage, tape & reel) ordering information design considerations the cat25cxxx powers up in a write disable state and in a low power standby mode. a wren instruction must be issued to perform any writes to the device after power up. also,on power up cs should be brought low to enter a ready state and receive an instruction. after a suc- cessful byte/page write or status register write the cat25cxxx goes into a write disable mode. cs must be set high after the proper number of clock cycles to start an internal write cycle. access to the array during an internal write cycle is ignored and programming is continued. on power up,so is in a high impedance. if an invalid op code is received, no data will be shifted into the cat25cxxx, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. the v cc sense provides write protection when v cc falls below the reset threshold value (v th ). the v cc lock out inhibits writes to the serial eeprom whenever v cc falls below (power down) v th or until v cc reaches the reset threshold (power up) v th . package p = pdip s = 8-pin soic s16 = 16-pin soic u14 = 14-pin tssop prefix device # suffix 25c16 s i te13 product number 25c32: 32k 25c16:16k 25c08: 8k 25c04: 4k 25c02: 2k tape & reel te13: 2000/reel cat temperature range blank = commercial (0?c to +70?c) i = industrial (-40?c to +85?c) a = automotive (-40? to +105?c)* * -40?c to +125?c is available upon request optional company id -30 reset threshold voltage 45: 4.5-4.75v 42: 4.25-4.5v 30: 3.0-3.15v 28: 2.85-3.0v 25: 2.55-2.7v 17: 1.7-1.8v 1 reset 1. reset 2. reset

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